In power amplification, the improvement of the power efficiency is important. When amplifying the power containing a desired fundamental wave with the power amplifier using a transistor, unnecessary power components of the harmonics of frequencies of integral multiples of the fundamental wave frequency are generated in addition to a fundamental wave power component having the fundamental wave frequency because the transistor is a non-linear device. When these unnecessary harmonic power components are consumed in the power amplifier, the power added efficiency of the power amplifier reduces.
As a method of preventing the power added efficiency from reducing by controlling the harmonic power components, a method of using the class-F amplification and the inverse class-F amplification is known. In the time-domain of the class-F amplification and the inverse class-F amplification, voltage and current are separated on the output side of the transistor. More specifically, in the class-F amplification, the voltage is a square wave, the current is a half sine wave, and the voltage and the current turn to a zero level alternately. On the contrary, in the inverse class-F amplification, the current is a square wave, the voltage is a half sine wave, and the voltage and the current turn to the zero level alternately.
FIG. 1A is a graph group showing an example of a time change of the current flowing into the transistor and the voltage generated at the output terminal of the transistor in the class-F amplifier. Here, the current flowing into the transistor is, for example, a drain current, and the voltage generated at the output terminal of the transistor is, for example, a voltage between the drain and the source. The graph group of FIG. 1A contains a first graph 1Ai showing the current flowing into the transistor and a second graph 1Av showing the voltage generated at the output terminal of the transistor. In FIG. 1A, the horizontal axis shows the time in unit of period of the fundamental wave and the vertical axis shows amplitudes of current and voltage. The current id(t) in the first graph 1Ai and the voltage vds(t) in the second graph 1Av are shown by the following equation (1).
                                                        i              d                        ⁡                          (              t              )                                =                                    1              π                        -                                          1                2                            ⁢              sin              ⁢                                                          ⁢                              ω                0                            ⁢              t                        -                                          2                π                            ⁢                                                ∑                                      m                    =                    1                                    5                                ⁢                                                      1                                                                  4                        ⁢                                                  m                          2                                                                    -                      1                                                        ⁢                  cos                  ⁢                                                                          ⁢                  2                  ⁢                                                                          ⁢                  m                  ⁢                                                                          ⁢                                      ω                    0                                    ⁢                  t                                                                    ⁢                                  ⁢                                            υ              ds                        ⁡                          (              t              )                                =                                    1              2                        ⁡                          [                                                1                  2                                +                                                      2                    π                                    ⁢                  sin                  ⁢                                                                          ⁢                                      ω                    0                                    ⁢                  t                                +                                                      2                    π                                    ⁢                                                            ∑                                              m                        =                        1                                            9                                        ⁢                                                                  1                                                                              2                            ⁢                            m                                                    +                          1                                                                    ⁢                                              sin                        ⁡                                                  (                                                                                    2                              ⁢                              m                                                        +                            1                                                    )                                                                    ⁢                                              ω                        0                                            ⁢                      t                                                                                  ]                                                          (        1        )            
As shown in the example of FIG. 1A, in the transistor of the class-F amplifier, when the voltage between the drain and the source is generated, a drain current is turned to a zero level, and on the contrary, when the drain current is generated, the voltage between the drain and the source is turned to the zero level. Therefore, the power consumed in the transistor of the class-F amplifier is zero, and the average power consumption is also zero. As a result, in the class-F amplifier, the power efficiency of 100% is obtained theoretically. The characteristics are the same as in the inverse class-F amplifier.
In conjunction with the above, Patent Literature 1 (Japanese Patent No. 4,335,633) discloses the technique of a class-F amplification circuit and an addition circuit for the class-F amplifier. This class-F amplification circuit is composed of a transistor and a load circuit disposed at a rear stage of the transistor. The load circuit is composed of a first reactance two-terminal circuit and a second reactance two-terminal circuit. Impedance of each of the circuits has the zero in the even-order harmonic and a pole in the odd-order harmonic according to need.
Also, Patent Literature 2 (JP 2011-55152A) discloses the technique of an amplification circuit. The amplification circuit is composed of a transistor, a harmonic processing circuit disposed at the rear stage of the transistor, and a resonant circuit section disposed at the rear stage of the harmonic processing circuit. The transistor can be illustrated as an equivalent circuit which has a current source, a drain-source capacitance and a drain inductance. The harmonic processing circuit has a ladder-type circuit of n stages, each of which n stages contains a parallel capacitance and a serial inductor. Here, the n is an integer equal to or more than 1. The resonant circuit section has (2n+1) resonators whose resonance frequencies are different from each other. The resonance frequencies of the (2n+1) resonators frequency are coincident with the frequencies of the (n+1) zeros and n poles which are formed between the drain output section of the transistor and the ground when the output section of the harmonic processing circuit is short-circuited. The resonance frequencies of the 2n resonators of these (2n+1) resonators are respectively coincident with the frequencies of second to (2n+1)th harmonics.
Also, Patent Literature 3 (JP 2011-66839A) discloses a microwave harmonic processing circuit. The microwave harmonic processing circuit has a serial transmission line and a plurality of parallel open stubs connected to an output terminal of the serial transmission line in parallel with each other. The serial transmission line is connected with the output terminal of the transistor at the input terminal and has a predetermined electric length. The plurality of parallel open stubs have predetermined electric lengths to the second to nth harmonics. Here, the n is an optional integer and the total number of parallel open stubs is (n−1). The microwave harmonic processing circuit has a first transmission line layer, a second transmission line layer, a ground layer and vias. The first transmission line layer is configured from the serial transmission line and two of the (n−1) parallel open stubs which two are connected to one connection point. The second transmission line layer is configured from the (n−3) parallel open stubs excluding the above two parallel open stubs which are connected to a connection point. The ground layer is arranged between the first transmission line layer and the second transmission line layer. The via connects the connection point in the first transmission line layer and the connection point in the second transmission line layer electrically.